Responsibilities
- Execute assigned test cases according to the verification plan and debug issues encountered during testing.
- Extract and validate SVRNM (SystemVerilog Real Number Modeling) models of analog blocks.
- Develop and implement test cases using adice or UVM (Universal Verification Methodology) environment for various sections such as functional verification and test mode.
- Collaborate effectively with designers and other teams throughout the verification phase.
- File, track, and manage bugs to closure using Jira.
- Document results of assigned blocks comprehensively and participate actively in peer reviews.
Qualifications
- Completed university degree in Electronics Engineering or a related field.
- 5+ years of hands-on experience in chip-level Analog Mixed-Signal (AMS) verification of System on Chip (SOC).
- Proficient in independently debugging complex issues arising during verification.
- Familiarity and experience with mixed-signal simulators.
- Expertise in coding Analog Behavioral Models using SVRNM.
- Experience with Gate Level Simulation (GLS) and scan simulations at the top level is preferred.
- Basic understanding of SystemVerilog (SV) assertions is desirable.
- A team player with strong analytical and debugging skills.
- Experience with Analog Devices, Inc. (ADI) tools like adsim, adice, etc., would be advantageous.
This role requires a proactive individual with a deep understanding of analog and digital verification methodologies, strong coding skills, and the ability to work effectively both independently and within a team environment.