As a Principal Engineer specializing in Design for Test (DFT), you will lead the implementation, integration, and verification of System-on-Chip (SoC) projects from inception to production.
Responsibilities
- Guiding DFT implementation strategies, ensuring adherence to quality targets throughout the project lifecycle.
- Overseeing the development of DFT architecture and test pattern generation, encompassing Scan&ATPG, Memory BIST, Logic BIST, and Analog/PHY test methodologies.
- Collaborating with various teams including front-end design, verification, and physical design to ensure the delivery of high-quality silicon.
- Providing post-silicon support, collaborating closely with test engineering and validation teams to address any issues that arise.
Requirements
- A Master's or Bachelor's Degree in Electrical/Electronic Engineering.
- 10-12 years of experience in DFT, with a proven track record of delivering production-quality chips.
- Expertise in all facets of DFT, including scan & ATPG, memory BIST, logic BIST, analog test, and post-silicon support.
- Proficiency in the design flow, from specification and micro-architecture definition to design, verification, timing analysis, and physical design.
- Self-motivation and strong written and verbal communication skills.
- Exceptional problem-solving abilities, with the capacity to analyze complex issues and break them down into manageable components.
- A collaborative mindset, demonstrating the ability to work effectively within cross-functional teams to resolve issues and achieve project objectives.
Join Us
If you're ready to lead DFT initiatives at the forefront of SoC development and contribute to the creation of cutting-edge technologies, we invite you to apply for the Principal Engineer - DFT position in Bangalore. Join our dynamic team and embark on a rewarding journey of innovation and excellence.